The present invention relates to a static memory circuit incorporating memory cells of a MOS static type.
In general, each of the MOS static memory cells comprises a bi-stable flip-flop which uses four transistors per bit. That is, the memory cell comprises a pair of load resistors, a pair of driver transistors which are cross-coupled to each other, and a pair of transfer gate transistors connected to one word line and one bit line pair. In this memory cell, only one of the driver transistors is turned on to correspond to memory data "0" or "1".
In order to read the cell, the transfer gate transistors are turned on by changing the potential of the word line so that the data on the driver transistors is transferred to the bit lines. Similarly, in order to write data into the cell, the transfer gate transistors are also turned on by changing the potential of the word line and proper voltages are then applied to the bit lines.
One conventional static memory circuit of a MOS static type incorporates a large number of such memory cells arranged along rows and columns which are orthogonal to each other. In addition, the circuit comprises a plurality of word lines each connected to the memory cells belonging to one row, a plurality of pairs of bit lines, each pair connected to the memory cells belonging to one column, and a plurality of pairs of column selection gates each pair connected to one pair of the bit lines. In this case, selection of one cell among the memory cells is effected by selecting one of the word lines and one pair of the bit lines.
However, in the above-mentioned conventional circuit, when one memory cell is selected so as to read the data stored in the cell, transfer gate transistors of other non-selected memory cells belonging to the same word line of the selected cell are also turned on, so that currents flow from a power supply through the non-selected memory cells to another power supply (ground). In this case, such non-selected memory cells which are connected to one selected word line are defined as half-selected memory cells. Therefore, since a large number of such half-selected memory cells are connected to one selected word line, power dissipation therefor is large. In addition, even in non-selected memory cells which are connected to a non-selected word line, in order to maintain the memory data stored in the flip-flops of the non-selected memory cells, appropriate hold currents which are, of course, relatively small must flow therethrough. Therefore, since there are also a large number of such non-selected memory cells in the static memory circuit, power dissipation therefor is large.
It is a summary of the invention object of the present invention to provide a static memory circuit with small power dissipation and without reducing the read speed.
According to the present invention, there is provided a static memory circuit comprising: a first power supply; a second power supply the potential of which is lower than that of the first power supply; a plurality of word lines; a plurality of pairs of bit lines; a plurality of pairs of column selection gate transistors each pair connected to one of the pairs of bit lines and controlled by one of the column selection signals; a plurality of memory cells each comprising a pair of first loads connected to the first power supply, first and second transistors each having a gate connected to one of the first loads and to a drain of the other transistor, and each having a source connected to a source of the other transistor, and third and fourth transistors each having a drain connected to one of the bit lines, each having a source connected to one of the drains of the first and second transistors and each having a gate connected to one of the word lines; and a plurality of means, connected to the sources of the first and second transistors of the memory cells and to the second power supply, for setting the potential of the sources of the first and second transistors of a selected one of the memory cells to be lower than those of non-selected ones of the memory cells.
The present invention will now be more clearly understood from the following description contrasted with the conventional circuit and with reference to the drawings.